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4 Results  for Central Connecticut State University

Refined by: Creation Date: 1987 To 2002 remove Author/Creator: Halle, S remove
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1
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Article
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1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Rengarajan, R ; Boyong He ; Ransom, C ; Chang Ju Choi ; Ramachandran, R ; Haining Yang ; Butt, S ; Halle, S ; Yan, W ; Lee, K ; Chudzik, M ; Robl, W ; Parks, C ; Massey, J.G ; La Rosa, G ; Yujun Li ; Radens, C ; Divakaruni, R ; Crabbe, E

IEEE Electron Device Letters, October 2002, Vol.23(10), pp.621-623 [Peer Reviewed Journal]

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Conference Proceeding
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A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

Gruening, U ; Radens, C.J ; Mandelman, J.A ; Michaelis, A ; Seitz, M ; Arnold, N ; Lea, D ; Casarotto, D ; Knorr, A ; Halle, S ; Ivers, T.H ; Economikos, L ; Kudelka, S ; Rahn, S ; Tews, H ; Lee, H ; Divakaruni, R ; Welser, J.J ; Furukawa, T ; Kanarsky, T.S ; Alsmeier, J ; Bronner, G.B

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999, pp.25-28

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Nitride framed shallow trench isolation (NFSTI) for self-aligned buried strap in high performance trench capacitor DRAM/eDRAM

Kim, B ; Fukuzaki, Y ; Worth, G ; Nuetzel, J ; Williams, G ; Lee, B ; Takegawa, Y ; Halle, S ; Rupp, T ; Sudo, A ; Divakaruni, R ; Srinivasan, R ; Mii, T ; Bronner, G

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517), 2001, pp.89-92

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4
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Article
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Plasma-etching processes for ULSI semiconductor circuits

Armacost, M ; Hoh, P ; Wise, R ; Yan, W

IBM Journal of Research and Development, Jan-Mar 1999, Vol.43(1/2), pp.39-72 [Peer Reviewed Journal]

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4 Results  for Central Connecticut State University

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